A cache memory is a very fast local storage memory that is utilized by a central processing unit or a microprocessor. The cache memory fits into a system between the processor and the main system memory and operates as a "turbocharger" to the slower main system memory by holding copies of code and data that are frequently requested from the main system memory by the microprocessor. A cache memory system is typically made up of a cache RAM, a tag directory and cache management logic. The cahe RAM stores data or instructions which have been most recently used by the microprocessor and are therefore most likely to be needed again. The tag directory is usually a separate RAM array which hold address information and valid bits corresponding to the data in the cache RAM. The address information in the tag directory is referred to as the cache tag. The tag directory is primarily comprised of upper addresses in the overall CPU memory address which are compared with the address output by the microprocessor. If a match occurs, this indicates that data is stored in the cache RAM and the microprocessor does not have to go to the main system memory. When the data is present in the cache RAM, this is termed a "hit".
One of the advantages of cache is that the microprocessor can access data or instructions from the cache RAM without having to go to the system data and address bus. In general, when the microprocessor has to go to main memory, there are a number of "wait" states that must be programmed which essentially delay the operation of the microprocessor for a number of operating cycles in order to effect a data transfer. By utilizing the cache which operates at a much faster rate, the number of wait states for data transfer can be reduced to substantially zero.
The efficiency of the cache is traditionally measured in terms of the cache "hit rate". Hit rate is the measure of the cache's ability to maintain the most frequently used code and data requested by the microprocessor. A high hit rate means that the microprocessor spends a high percentage of its time working from the data cache RAM and a low percentage of its time requesting data from the slower main system DRAM memory. This results in a higher overall microprocessor performance.
There are a number of architectures that have been utilized with cache. One of these is referred to as a "look through" architecture and one is referred to as a "look aside" architecture. The look through architecture is a serial architecture whereas the look aside architecture is a parallel architecture. In the look through architecture, the cache is designed to fit in series between the microprocessor and the main system memory. The microprocessor "looks through" the cache to the main system memory. All memory requests from the microprocessor are first sent to the cache, then from the cache to the main system memory. The main advantage of a serial cache is that it will reduce the number of memory requests to main system DRAM memory. This reduces bus utilization of the main memory bus and the amount of memory precharge cycles (memory location setup locations). Most memory requests are handled directly out of cache without the need to access main system memory. Only when there is a cache miss is the memory request forwarded on to main system memory.
In a look aside cache, the cache is designed to fit on to the memory bus in parallel with the microprocessor and main system memory. The cache does not interrupt memory requests from the microprocessor to main system memory. Instead, all memory requests from the microprocessor are sent simultaneously to the cache and main system memory. The main microprocessor "looks aside" at the cache when sending memory requests to main system memory. If the cache hit occurs on a memory request, the cache returns the information to the microprocessor and sends a signal to the main system memory to abort the memory request. If a cache miss occurs, the cache does nothing. The memory request is completed by the main system memory.
One disadvantage to a cache memory is size constraints. In order to provide sufficient speed, most cache memories are fabricated from Static Random Access Memories (SRAM). One problem with SRAM is that it takes a substantial amount of real estate and therefore, large arrays cannot be realized. If DRAM arrays are utilized in place of SRAM arrays, a higher density can be achieved with some sacrifice in speed. Typically, an SRAM can be utilized in a cache system with zero wait states, whereas DRAM would require one or two wait states, depending upon the speed thereof. More than two wait states may be required in order to interface with the system bus.